LAN9500AI datasheet(116/213 Pages) MICROCHIP

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LAN950x

DS00001875A-page 116

 2010 - 2015 Microchip Technology Inc.

7.0

7.1

Table 7-1 describes the register bit attributes used throughout this document.

7.2

TABLE 7-1:

Type Notation

Read: A register or bit with this attribute can be read.

Write: A register or bit with this attribute can be written.

Read only: Read only. Writes have no effect.

Read to Set: This bit is set on read.

Write only: If a register or bit is write-only, reads will return unspecified data.

Write One to Clear: writing a one clears the value. Writing a zero has no effect.

WAC

Write Anything to Clear: writing anything clears the value.

Read to Clear: Contents is cleared after the read. Writes have no effect.

Latch Low: Clear on read of register.

Latch High: Clear on read of register.

Self-Clearing: Contents is self-cleared after the being set. Writes of zero have no

effect. Contents can be read.

RO/LH

Read Only, Latch High: This mode is used by the Ethernet PHY registers. Bits with

this attribute will stay high until the bit is read. After it a read, the bit will remain high,

but will change to low if the condition that caused the bit to go high is removed. If the

bit has not been read the bit will remain high regardless of if its cause has been

removed.

NASR

Not Affected by Software Reset. The state of NASR bits does not change on

assertion of a software reset.

RESERVED

Reserved Field: Reserved fields must be written with zeros, unless otherwise

indicated, to ensure future compatibility. The value of reserved bits is not guaranteed

on a read.

TABLE 7-2:

LAN950X REGISTER MEMORY MAP

Address

Symbol

000h - 0FFh

SCSR

System Control and Status Registers

100h - 1FCh

MCSR

MAC Control and Status Registers

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