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CP3SP33SMS/NOPB Datasheet(PDF) 225 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 225 Page - Texas Instruments |
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225 / 407 page ![]() Shift Data (STD/SRD) High-impedance Unused Slots Slot1 Frame Slot0 Long Frame Sync (SFS/SRFS) Data (ignored) Data (ignored) Data (valid) DS055 CP3SP33 www.ti.com SNOSCW5 – MAY 2013 Figure 24-3. Network Mode Frame 24.2.3.4 Interrupt Support If DMA is not enabled for a receive slot n (RXDSAn = 0), all data received in this slot is loaded into the receive FIFO. The interrupt request is asserted as soon as the number of data bytes or words in the receive FIFO is greater than a programmable warning limit. If DMA is not enabled for a transmit slot n (TXDSAn = 0), all data to be transmitted in this slot are read from the transmit FIFO. The interrupt request is asserted as soon as the number data bytes or words available in the transmit FIFO is equal or less than a programmable warning limit. Because the interrupt request can be handled by either the CPU or DSP interrupt controllers, the interrupt request is passed through the Audio Subsystem Controller (ASC), which is programmed to route it to the interrupt controller. To use the codec interrupt, it must be enabled at three levels: • AAI module—the interrupt must be enabled in the AISCR register. • ASC module—the AAI interrupt is assigned to ASC interrupt channel 7, so bit 7 in the ASCINTSEL register must be clear to select CPU interrupt controller or set to select the DSP interrupt controller • Interrupt controller—the interrupt request must be enabled in the interrupt controller. For the CPU interrupt controller, this is interrupt request IRQ27 24.2.3.5 DMA Support If DMA support is enabled for a receive slot n (RXDSA0 = 1), all data received in this slot is only transferred from the ARSR into the corresponding DMA receive register (ARDRn). A DMA request is asserted when the ARDRn register is full. If DMA is enabled for a transmit slot n (TXDSAn = 1), all data to be transmitted in slot n are read from the corresponding DMA transmit register (ATDRn). A DMA request is asserted to the DMA controller when the ATDRn register is empty Figure 24-4 illustrates the data flow for IRQ and DMA support in network mode, using four slots per frame and DMA support enabled for slots 0 and 1 in receive and transmit direction. Copyright © 2013, Texas Instruments Incorporated Advanced Audio Interface 225 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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