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CP3SP33SMS/NOPB Datasheet(PDF) 389 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 389 Page - Texas Instruments |
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389 / 407 page  I2SCLK I2SWS, I2SSDI, I2SSDO DS370 tCH tCL T tTH tRS tRH tTD tCR CP3SP33 www.ti.com SNOSCW5 – MAY 2013 36.13 USB Port AC Characteristics Table 36-8. USB Port Signals DESCRIPTION(1) CONDITIONS(2) MIN TYP MAX UNIT TR Rise time CL = 50 pF 4 20 ns TF Fall Time CL = 50 pF 4 20 ns TRFM Fall/Rise time matching (TR/TF) CL = 50 pF 90% 110% ZDRV Driver Output Impedance CL = 50 pF 28 43 Ω (1) Specified by design. (2) Waveforms measured at 10% to 90%. 36.14 I 2S Interface Timing Table 36-9. I2S Interface Signals LOWER LIMIT UPPER LIMIT DESCRIPTION(1) REFERENCE UNIT MIN MAX MIN MAX I2S INTERFACE TRANSMITTER SIGNALS T See Figure 36-22 Tt ns I2S clock period Tt Minimum transmitter clock period T > Tt, See Figure 36-22 ns 0.35 Tt 0.35 Tt tCH Vih, See Figure 36-22 ns I2S clock high (master) (slave) 0.35 Tt 0.35 Tt tCL Vil, See Figure 36-22 ns I2S clock low (master) (slave) tCR See Figure 36-22 0.15 Tt ns I2S clock rise time (slave mode) Rising Edge (RE) on I2S Clock, See tTD Delay 0.8 Tt ns Figure 36-22 tTH Hold time 0 ns RE on I2S Clock, See Figure 36-22 I2S INTERFACE RECEIVER SIGNALS T See Figure 36-22 Tt ns I2S clock period Tr Minimum receiver clock period T > Tt, See Figure 36-22 ns 0.35 Tr 0.35 Tr tCH Vih, See Figure 36-22 ns I2S clock high (master) (slave) 0.35 Tr 0.35 Tr tCL Vil, See Figure 36-22 ns I2S clock low (master) (slave) tRS Setup time 0.2 Tr ns RE on I2S Clock tRH Hold time 0 RE on I2S Clock (1) Specified by design. Figure 36-22. I2S Interface Timing Copyright © 2013, Texas Instruments Incorporated Electrical Specifications 389 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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