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CP3SP33SMS/NOPB Datasheet(PDF) 391 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 391 Page - Texas Instruments

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background image
XCSn
HCLK
DS456
XAn
XWE
XBEn
XDn
Data
Address
tAV
tCSL
tBEL
tAH
tCSH
tBEH
tWEL
tDOV
tDOH
tWEH
XCSn
HCLK
DS455
XAn
XOE
XBEn
XDn
Data
Address
tAV
tCSL
t
BEL
tOEL
tAH
tCSH
t
BEH
tOEH
tDIH
tDSU
CP3SP33
www.ti.com
SNOSCW5 – MAY 2013
Table 36-12. External Memory Signals (continued)
DESCRIPTION(1)
REFERENCE
MIN
MAX
UNIT
tBEL
Byte Enable Low
After RE on HCLK Clock, See Figure 36-25 and Figure 36-26
9
ns
tBEH
Byte Enable Hold
After RE on HCLK Clock, See Figure 36-25 and Figure 36-26
0
ns
tOEL
Output Enable Low
After RE on HCLK Clock, See Figure 36-25
9
ns
tOEH
Output Enable Hold
After RE on HCLK Clock, See Figure 36-25
0
ns
tWEL
Write Enable Low
After RE on HCLK Clock, See Figure 36-26
9
ns
tWEH
Write Enable Hold
After RE on HCLK Clock, See Figure 36-26
0
ns
tDOV
Data Bus Output Valid
After RE on HCLK Clock, See Figure 36-26
9
ns
tDOH
Data Bus Output Hold
After RE on HCLK Clock, See Figure 36-26
0
ns
Figure 36-25. Memory Read Cycle
Figure 36-26. Memory Write Cycle
Copyright © 2013, Texas Instruments Incorporated
Electrical Specifications
391
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