CP3SP33SMSSLASHNOPB datasheet(390/407 Pages) TI1

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TIOL

TIOH

PCLK

TIOn_y

DS482

tTAL /tTBL

PCLK

TAn/TBn

DS481

tTAL /tTBH

CP3SP33

SNOSCW5 – MAY 2013

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36.15 Multi-Function Timer (MFT) Timing

Table 36-10. Multi-Function Timer Input Signals

DESCRIPTION(1)

REFERENCE

MIN

MAX

UNIT

tTAH

TAn high time

Rising edge (RE) on PCLK clock, See Figure 36-23

TCLK + 5

tTAL

TAn low time

RE on PCLK clock, See Figure 36-23

TCLK + 5

tTBH

TBn high time

RE on PCLK clock, See Figure 36-23

TCLK + 5

tTBL

TBn low time

RE on PCLK clock, See Figure 36-23

TCLK + 5

(1)

Specified by design.

Figure 36-23. Multi-Function Timer Input Timing

36.16 Versatile Timing Unit (VTU) Timing

Table 36-11. Versatile Timing Unit Input Signals

DESCRIPTION(1)

REFERENCE

MIN

MAX

UNIT

tTIOH

TIOn_y Input High Time

Rising Edge (RE) on PCLK Clock, See Figure 36-

1.5 × TCLK + 5

tTIOL

TIOn_y Input Low Time

RE on PCLK Clock, See Figure 36-24

1.5 × TCLK + 5

(1)

Specified by design.

Figure 36-24. Versatile Timing Unit Input Timing

36.17 External Memory Interface

Table 36-12. External Memory Signals

DESCRIPTION(1)

REFERENCE

MIN

MAX

UNIT

EXTERNAL MEMORY INPUT SIGNALS

tDSU

Data Bus Input Setup

Before Rising Edge (RE) on HCLK Clock, See Figure 36-25

tDIH

Data Bus Input Hold

After RE on HCLK Clock , See Figure 36-25

EXTERNAL MEMORY OUTPUT SIGNALS

tAV

Address Bus Valid

After RE on HCLK Clock, See Figure 36-25 and Figure 36-26

tAH

Address Bus Hold

After RE on HCLK Clock, See Figure 36-25 and Figure 36-26

tCSL

Chip Select Low

After RE on HCLK Clock, See Figure 36-25 and Figure 36-26

tCSH

Chip Select Hold

After RE on HCLK Clock, See Figure 36-25 and Figure 36-26

(1)

Specified by design.

390

Electrical Specifications

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