M38B53M4-059FP datasheet(263/355 Pages) MITSUBISHI

263 / 355 page

38B5 Group User’s Manual

3-15

APPENDIX

3.3 Notes on use

(3)

Structure of interrupt control register 2

Fix the bit 7 of the interrupt control register 2

to “0”. Figure 3.3.3 shows the structure of the

interrupt control register 2.

Fig. 3.3.3 Structure of interrupt control register 2

3.3.2 Notes on serial I/O1

(1) Clock

s Using internal clock

After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit

before perform the normal serial I/O transfer or the serial I/O automatic transfer.

s Using external clock

After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit

before performing the normal serial I/O transfer or the serial I/O automatic transfer.

(2) Using serial I/O1 interrupt

Clear bit 3 of the interrupt request register 1 to “0” by software.

(3)

State of SOUT1 pin

The SOUT1 pin control bit of the serial I/O1 control register 2 can be used to select the state of the

SOUT1 pin when serial data is not transferred; either output active or high-impedance. However, when

selecting an external synchronous clock; the SOUT1 pin can become the high-impedance state by

setting the SOUT1 pin control bit to “1” when the serial I/O1 clock input is at “H” after transfer completion.

(4)

Serial I/O initialization bit

q Set “0” to the serial I/O initialization bit of the serial I/O1 control register 1 when terminating a

serial transfer during transferring.

q When writing “1” to the serial I/O initialization bit, the serial I/O1 is enabled, but each register is

not initialized. Set the value of each register by program.

(5)

Handshake signal

s SBUSY1 input signal

Input an “H” level to the SBUSY1 input and an “L” level signal to the SBUSY1 input in the initial state.

When the external synchronous clock is selected, switch the input level to the SBUSY1 input and

the SBUSY1 input while the serial I/O1 clock input is in “H” state.

s SRDY1 input•output signal

When selecting the internal synchronous clock, input an “L” level to the SRDY1 input and an “H”

level signal to the SRDY1 input in the initial state.

(6)

8-bit serial I/O mode

s When selecting external synchronous clock

When an external synchronous clock is selected, the contents of the serial I/O1 register are being

shifted continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control

the clock externally.

Interrupt control register

Address 003F16

Interrupt enable bits

Not used

Fix this bit to “0”.

M38B53M4-059FP Datasheet(PDF) 263 Page - Mitsubishi Electric Semiconductor

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