M38B53M4-059FP datasheet(264/355 Pages) MITSUBISHI

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3-16

APPENDIX

38B5 Group User’s Manual

3.3 Notes on use

(7)

In automatic transfer serial I/O mode

s Set of automatic transfer interval

q When the SBUSY1 output is used, and the SBUSY1 output and the SSTB1 output function as signals

for each transfer data set by the SBUSY1 output•SSTB1 output function selection bit of serial I/O1

control register 2; the transfer interval is inserted before the first data is transmitted/received,

and after the last data is transmitted/received. Accordingly, regardless of the contents of the

SBUSY1 output•SSTB1 output function selection bit, this transfer interval for each 1-byte data becomes

2 cycles longer than the value set by the automatic transfer interval set bits of serial I/O1 control

q When using the SSTB1 output, regardless of the contents of the SBUSY1 output•SSTB1 output function

selection bit, this transfer interval for each 1-byte data becomes 2 cycles longer than the value

set by the automatic transfer interval set bits of serial I/O1 control register 3.

q When using the combined output of SBUSY1 and SSTB1 as the signal for each of all transfer data

set, the transfer interval after completion of transmission/reception of the last data becomes 2

cycles longer than the value set by the automatic transfer interval set bits.

q Set the transfer interval of each 1-byte data transfer to 5 or more cycles of the internal clock

φ after the rising edge of the last bit of a 1-byte data.

q When selecting an external clock, the set of automatic transfer interval becomes invalid.

s Set of serial I/O1 transfer counter

q Write the value decreased by 1 from the number of transfer data bytes to the serial I/O1 transfer

counter.

q When selecting an external clock, after writing a value to the serial I/O1 register/transfer counter,

wait for 5 or more cycles of internal clock

φ before inputting the transfer clock to the serial I/

O1 clock pin.

s Serial I/O initialization bit

A serial I/O1 automatic transfer interrupt request occurs when “0” is written to the serial I/O

initialization bit during an operation. Disable it with the interrupt enable bit as necessary by program.

3.3.3 Notes on serial I/O2

(1)

Notes when selecting clock synchronous serial I/O

Stop of transmission operation

As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)

serial I/O, clear the transmit enable bit to “0” (transmit disabled).

q Reason

Since transmission is not stopped and the transmission circuit is not initialized even if only the

serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running

(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission

data is not output). When data is written to the transmit buffer register in this state, data starts to

be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,

the data during internally shifting is output to the TxD pin and an operation failure occurs.

Stop of receive operation

As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)

serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O2 enable bit

to “0” (serial I/O2 disabled).

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