M38B53M4-059FP datasheet(265/355 Pages) MITSUBISHI

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38B5 Group User’s Manual

3-17

APPENDIX

3.3 Notes on use

Stop of transmit/receive operation

As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)

serial I/O, simultaneously clear both the transmit enable bit and receive enable bit to “0” (transmit

and receive disabled).

(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data

transmission and reception cannot be stopped.)

q Reason

In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.

If any one of transmission and reception is disabled, a bit error occurs because transmission and

reception cannot be synchronized.

In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,

the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit

disabled). Also, the transmission circuit is not initialized by clearing the serial I/O2 enable bit to

“0” (serial I/O2 disabled) (refer to (1), ).

(2)

Notes when selecting clock asynchronous serial I/O

Stop of transmission operation

As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)

serial I/O, clear the transmit enable bit to “0” (transmit disabled).

q Reason

Since transmission is not stopped and the transmission circuit is not initialized even if only the

serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running

(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission

data is not output). When data is written to the transmit buffer register in this state, data starts to

be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,

the data during internally shifting is output to the TxD pin and an operation failure occurs.

Stop of receive operation

As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)

serial I/O, clear the receive enable bit to “0” (receive disabled).

Stop of transmit/receive operation

Only transmission operation is stopped.

As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)

serial I/O, clear the transmit enable bit to “0” (transmit disabled).

q Reason

Since transmission is not stopped and the transmission circuit is not initialized even if only the

serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running

(in this case, since pins TxD, RxD, SCLK21, SCLK22 and SRDY2 function as I/O ports, the transmission

data is not output). When data is written to the transmit buffer register in this state, data starts to

be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,

the data during internally shifting is output to the TxD pin and an operation failure occurs.

Only receive operation is stopped.

As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)

serial I/O, clear the receive enable bit to “0” (receive disabled).

(3)

SRDY2 output of reception side

When signals are output from the SRDY2 pin on the reception side by using an external clock in the

clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY2 output enable bit, and

the transmit enable bit to “1” (transmit enabled).

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