M38B53M4-059FP datasheet(268/355 Pages) MITSUBISHI

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3-20

APPENDIX

38B5 Group User’s Manual

3.3 Notes on use

3.3.7 Notes on watchdog timer

q The watchdog timer continues to count even while waiting for stop release. Accordingly, make sure that

watchdog timer does not underflow during this term by writing to the watchdog timer control register

(address 002B16) once before executing the STP instruction, etc.

q Once a “1” is written to the STP instruction disable bit (bit 6) of the watchdog timer control register

(address 002B16), it cannot be programmed to “0” again. This bit becomes “0” after reset.

3.3.8 Notes on reset circuit

(1)

Reset input voltage control

Make sure that the reset input voltage is 0.5 V or less for Vcc of 2.7 V.

Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.

(2)

Countermeasure when RESET signal rise time is long

In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the

RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When

connecting the capacitor, note the following :

• Make the length of the wiring which is connected to a capacitor as short as possible.

• Be sure to verify the operation of application products on the user side.

q Reason

If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may

cause a microcomputer failure.

3.3.9 Notes on input and output pins

(1)

Notes in stand-by state

In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O

port “undefined”, especially for I/O ports of the N-channel open-drain.

Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a

resistor.

When determining a resistance value, note the following points:

• External circuit

• Variation of output levels during the ordinary operation

When using built-in pull-up resistor, note on varied current values:

• When setting as an input port : Fix its input level

• When setting as an output port : Prevent current from flowing out to external

q Reason

Even when setting as an output port with its direction register, in the following state :

• P-channel......when the content of the port latch is “0”

• N-channel......when the content of the port latch is “1”

the transistor becomes the OFF state, which causes the ports to be the high-impedance state.

Note that the level becomes “undefined” depending on external circuits.

Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the

state that input levels of a input port and an I/O port are “undefined”. This may cause power

source current.

*1 stand-by state : the stop mode by executing the STP instruction

the wait mode by executing the WIT instruction

M38B53M4-059FP Datasheet(PDF) 268 Page - Mitsubishi Electric Semiconductor

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