ST25R3910 datasheet(17/65 Pages) STMICROELECTRONICS

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ST25R3910

Functional overview

At power-up the regulated voltage is set to its maximum, i.e. 3.4 V.

The regulator voltage can then be set automatically or “manually”. The automatic procedure

is started by sending the direct command Adjust Regulators. In this procedure regulated

voltage is set 250 mV below VDD. This procedure ensures that reader operates with

maximum possible power while still achieving a good PSRR.

Regulator operation can be controlled and observed by writing and reading two Regulator

registers. Regulator Display Register is a read only register that displays actual regulated

voltage when regulator is operating. In Power-down mode its content is forced to 00.

By writing Regulated Voltage Definition Register the user chooses between automatic and

“manual” adjustment of regulated voltage. Automatic mode is chosen when bit reg_s is 0

(default and also recommended state). When bit reg_s is asserted to 1 regulated voltage is

defined by bits rege_3 to rege_0 of the same register.

1.2.9

Communication with an external microcontroller

The ST25R3910 is a slave devices and the external microcontroller initiates all

communication. Communication is performed by a 4-wire Serial Peripheral Interface (SPI).

The ST25R3910 sends an interrupt request (pin INTR) to the microcontroller, which can use

clock signal available on pin MCU_CLK when the oscillator is running. The microcontroller

can also drive pin EN. Putting this pin high has the same function as setting the Operation

Control Register bit en (entry in Ready mode).

Serial Peripheral Interface (SPI)

While signal SEN is low the SPI interface is in reset, while it is high the SPI is enabled. It is

recommended to keep SEN low whenever the SPI is not in use. SDATAI is sampled at the

falling edge of SCLK. All communication is done in blocks of 8 bits (bytes). First two bits of

first byte transmitted after low to high transition of SEN define SPI operation mode.

MSB bit is always transmitted first (valid for address and data).

Read and Write modes support address auto-incrementing. This means that if some

additional data bytes are sent/read after the address and first data byte, they are written

to/read from addresses incremented by ‘1’. Figure 4 defines possible modes.

Table 1. Serial data interface (4-wire interface) signal lines

Name

Signal

Signal level

Description

SEN

Digital input

CMOS

SPI Enable (active low)

SDATAI

Digital input

Serial data input

SDATAO

Digital output with tristate

Serial data output

SCLK

Digital input

Clock for serial communication

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