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ST25R3911B Datasheet(PDF) 13 Page - STMicroelectronics |
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ST25R3911B Datasheet(HTML) 13 Page - STMicroelectronics |
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13 / 129 page ![]() DocID029656 Rev 2 13/129 ST25R3911B Functional overview 71 1.1.11 ISO-14443 and NFCIP-1 framing This block performs framing for receive and transmit according to the selected ISO mode and bit rate settings. In reception it takes the demodulated sub-carrier signal from the receiver. It recognizes the SOF, EOF and data bits, performs parity and CRC check, organizes the received data in bytes and places them in the FIFO. During transmit, it operates inversely, it takes bytes from the FIFO, generates parity and CRC bits, adds SOF and EOF and performs final encoding before passing the modulation signal to the transmitter. In Transparent mode, the framing and FIFO are bypassed, the digitized sub-carrier signal (the receiver output), is directly sent to the MISO pin, and the signal applied to the MOSI pin is directly used to modulate the transmitter. 1.1.12 FIFO The ST25R3911B contains a 96-byte FIFO. Depending on the mode, it contains either data that has been received or data to be transmitted. 1.1.13 Control logic The control logic contains I/O registers that define operation of device. 1.1.14 SPI A 4-wire Serial Peripheral Interface (SPI) is used for communication between the external microcontroller and the ST25R3911B. 1.2 Application information The minimum configurations required to operate the ST25R3911B are shown in Figure 2 and Figure 3. |
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