ST25R3911B datasheet(39/129 Pages) STMICROELECTRONICS

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ST25R3911B

Functional overview

sources detailed in Timer and NFC Interrupt Register and Error and Wake-Up Interrupt

When an interrupt condition is met the source of interrupt bit is set in the Main Interrupt

The microcontroller then reads the Main Interrupt Register to distinguish between different

interrupt sources. The interrupt registers 0x17, 0x18 and 0x19 are to be read in one attempt.

After a particular Interrupt register is read, its content is reset to 0. Exceptions to this rule are

the bits pointing to auxiliary registers. These bits are only cleared when corresponding

auxiliary register is read. IRQ pin transitions to low after the interrupt bit(s) that caused its

transition to high has (have) been read.

Note:

There may be more than one interrupt bit set in case the microcontroller does not

immediately read the interrupt registers after the IRQ signal has been set and another event

causing interrupt has occurred. In that case the IRQ pin transitions to low after the last bit

that caused interrupt is read.

If an interrupt from a certain source is not required, it can be disabled by setting

corresponding bit in the Mask Interrupt registers. When masking a given interrupt source the

interrupt is not produced, but the source of interrupt bit is still set in Interrupt registers.

FIFO water level and FIFO status registers

The ST25R3911B contains a 96 byte FIFO. In case of transmitting the Control logic shifts

the data that was previously loaded by the external microcontroller to the Framing Block and

further to the transmitter. During reception, the demodulated data is stored in the FIFO and

the external microcontroller can download received data at a later moment.

Transmit and receive capabilities of the ST25R3911B are not limited by the FIFO size due to

a FIFO water level interrupt system. During transmission an interrupt is sent (IRQ due to

FIFO water level in the Main Interrupt Register) when the content of data in the FIFO passes

from (water level + 1) to water level and the complete transmit frame has not been loaded in

the FIFO yet. The external microcontroller can now add more data in the FIFO. The same

stands for the reception: when the number of received bytes passes from (water level - 1) to

water level an interrupt is sent to inform the external controller that data has to be

downloaded from FIFO in order not to lose receive data due to FIFO overflow.

During transmission water level IRQ is additionally set in case all transmission bytes have

not been written in FIFO yet and if number of bytes written into FIFIO is lower than water

level. In this case an IRQ is sent when number of bytes in FIFO drops below 4.

Note:

FIFO IRQ is not produced while SPI is active in FIFO load or read mode. Due to this the

FIFO loading/reading rate has to be higher than Tx/Rx bit rate, once FIFO loading/reading is

finished the /SS pin has to be pulled to VDD (logic remains in FIFO load/read mode as long

as /SS remains low).

In case controller knows that the receive data frame is smaller than the FIFO size the water

level interrupt does not have to be served. In such case the water level interrupt can be

masked.

Table 8. IRQ output

Name

Signal

Signal level

Description

IRQ

Digital output

CMOS

Interrupt output pin

ST25R3911B Datasheet(PDF) 39 Page - STMicroelectronics

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