MPF5023AMBA0ES datasheet(20/91 Pages) NXP

20 / 91 page

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

PF5023

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

20 / 91

14.5 Power up

14.5.1 Power up events

Upon a power cycle (VIN > UVDET), the LPM_OFF bit is reset to 0, therefore the device

moves to the LP_Off state by default. The actual value of the LPM_OFF bit can be

changed during the Run mode and is maintained until VIN crosses the UVDET threshold.

In either one of the Off modes, the PF5023 can be enabled by the following power up

events:

1. When OTP_PWRON_MODE = 0, PWRON pin is pulled high.

2. When OTP_PWRON_MODE = 1, PWRON pin experiences a high to low transition

and remains low for as long as the PWRON_DBNC timer.

A power up event is valid only if:

• VIN > UVDET

• VIN < VIN_OVLO (unless the OVLO is disabled or OTP_VIN_OVLO_SDWN = 0)

• Tj < thermal shutdown threshold

• TRIM_NOK = 0 && OTP_NOK = 0 && STEST_NOK = 0

14.5.2 Power up sequencing

The power up sequencer controls the time and order in which the voltage regulators and

other controlling I/O are enabled when going from the Off mode into the run state.

The OTP_SEQ_TBASE[1:0] bits set the default time base for the power up and power

down sequencer.

The SEQ_TBASE[1:0] bits can be modified during the system On state in order to

change the sequencer timing during run/standby transitions as well as the power down

sequence.

Table 17. Power up time base register

OTP bits

OTP_SEQ_TBASE[1:0]

Functional bits

SEQ_TBASE[1:0]

Sequencer time base

(µs)

120

250

500

The power up sequence may include any of the following:

• Switching regulators

• PGOOD pin if programmed as a GPO

• RESETBMCU

The default sequence slot for each one of these signals is programmed via the OTP

configuration registers. They can be modified in the functional I2C register map to change

the order in which the sequencer behaves during the run/standby transitions as well as

the power down sequence.

The x_SEQ[7:0] bits set the regulator/pin sequence from 0 to 254. Sequence code 0x00

indicates that the particular output is not part of the startup sequence and remains in OFF

(in case of a regulator) or remains low/disabled (in case PGOOD pin used as a GPO).

MPF5023AMBA0ES Datasheet(PDF) 20 Page - NXP Semiconductors

MPF5023AMBA0ES Datasheet(HTML) 20 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datasheet Download

Link URL