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MPF5023AMBA0ES Datasheet(PDF) 39 Page - NXP Semiconductors |
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MPF5023AMBA0ES Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 91 page ![]() NXP Semiconductors PF5023 Power management integrated circuit (PMIC) for high performance applications PF5023 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 39 / 91 14.9.7 PGOODx The PGOODx pins are open drain outputs to provide the power good status of each regulator. In the application, PGOODx can be pulled up to VDDIO with a 100 kΩ resistor. The PGOODx pin is pulled low when the corresponding regulator output falls above or below the programmed OV/UV thresholds. The actual condition causing the interrupt (OV, UV) can be read in the fault interrupt registers. For more details on handling interrupts, see Section 14.8 "Interrupt management". Table 31. PGOODx assignment Pin PF5023 regulator PGOOD1 SW1 PGOOD2 SW2 PGOOD3 SW3 14.9.8 ENx The ENx input pin is used to enable or disable the dedicated regulator via hardware. When the ENx pin is asserted low, the corresponding regulator is turned off. Table 32. ENx assignment Pin PF5023 regulator EN1 SW1 EN2 SW2 EN3 SW3 The status of the ENx pin can be monitored via the corresponding ENx_S flag bit in the EN SENSE register. • When ENx is in low state, ENx_S flag is set to 0. • When ENx is in high state, ENx_S flag is set to 1. 14.9.9 TBBEN The TBBEN is an input pin provided to allow the user to program the mirror registers in order to operate the device with a custom configuration as well as programming the default values on the OTP fuses. • When TBBEN pin is pulled low to ground, the device is operating in normal mode. • When TBBEN pin is pulled high to V1P5D, the device enables the TBB configuration mode. See Section 17 "OTP/TBB and hardwire default configurations" for details on TBB and OTP operation. When TBBEN pin is pulled high to V1P5D the following conditions apply: • The device uses a fixed I2C device address (0x08) • Disable the watchdog operation, including WDI monitoring and internal watchdog timer • Disable the CRC and I2C secure write mechanism while no power up event is present (TBB/OTP programming mode). |
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