MPF5023AMBA0ES datasheet(6/91 Pages) NXP

6 / 91 page

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

PF5023

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Product data sheet

Rev. 1 — 15 April 2020

6 / 91

Symbol

Parameter

Min

Typ

Max

Unit

VESD

Charge device model

All pins

[1]

—

500

ILATCHUP

Latch-up current

—

100

[1]

ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),

robotic (CZAP = 4.0 pF).

10 Thermal characteristics

Table 5. Thermal characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Ambient operating temperature

−40

—

125

°C

Junction temperature

−40

—

150

°C

TST

Storage temperature range

−40

—

150

°C

TPPRT

Peak package reflow temperature

—

260

°C

Table 6. QFN40 thermal resistance and package dissipation ratings

Symbol

Parameter

Typ

Unit

RθJA

Junction to Ambient Thermal Resistance

JESD51-7, 2s2p

[1] [2] [3] 32.6

°C/W

RθJA

Junction to Ambient Thermal Resistance

JESD51-7, 2s6p

[1] [2] [4] 26.8

°C/W

ΨJT

Junction to Top of Package Thermal Parameter

JESD51-7, 2s2p

[1] [2] [3] 0.46

°C/W

ΨJT

Junction to Top of Package Thermal Parameter

JESD51-7, 2s6p

[1] [2] [4] 0.39

°C/W

[1]

Determined in accordance to JEDEC JESD51-2A natural convection environment and uniform power.

[2]

Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment.

It is not meant to predict the performance of a package in an application-specific environment.

[3]

Thermal test board meets JEDEC specification for this package (JESD51-7, 2s2p). PCB has a 3×3 array of thermal via under the exposed pad.

[4]

2s6p PCB identical to 51-7 but with four additional internal layers at 35 µm thickness.

11 Operating conditions

Table 7. Operating conditions

Symbol

Parameter

Min

Typ

Max

Unit

VIN

Main input supply voltage

UVDET

—

5.5

12 General description

12.1 Features

The PF5023 is a power management integrated circuit (PMIC) designed to be the

primary power management building block for NXP high-end multimedia application

processors from the i.MX 8 and S32V series. It is also capable of providing power

solution to the high end i.MX 6 series as well as several non-NXP processors.

• Buck regulators

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