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MPF5023AMBA0ES Datasheet(PDF) 70 Page - NXP Semiconductors

Part # MPF5023AMBA0ES
Description  Power management integrated circuit (PMIC) for high performance applications
PDF  91 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF5023AMBA0ES Datasheet(HTML) 70 Page - NXP Semiconductors

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NXP Semiconductors
PF5023
Power management integrated circuit (PMIC) for high performance applications
PF5023
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1 — 15 April 2020
70 / 91
MR
ADDR
FUSE
ADDR
Register name BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BD
1D
OTP SW4
PWRUP
Reserved
BE
1E
OTP SW4
CONFIG1
Reserved
Reserved
Reserved
Reserved
BF
1F
OTP SW4
CONFIG2
Reserved
Reserved
—
Reserved
Reserved
C0
20
OTP SWND1_
VOLT
—
—
—
Reserved
C1
21
OTP SWND1
PWRUP
Reserved
C2
22
OTP SWND1
CONFIG1
Reserved
Reserved
Reserved
Reserved
C3
23
OTP SWND1
CONFIG2
Reserved
Reserved
—
Reserved
Reserved
C4
24
OTP LDO1
VOLT
Reserved
Reserved
Reserved
C5
25
OTP LDO1
PWRUP
Reserved
C6
26
OTP LDO1
CONFIG
Reserved
—
—
—
Reserved
Reserved
Reserved
C7
27
OTP VSNVS
CONFIG
—
—
—
—
—
—
Reserved
C8
28
OTP_OV_
BYPASS1
—
Reserved
—
—
Reserved
OTP_SW3_
OVBYPASS
OTP_SW2_
OVBYPASS
OTP_SW1_
OVBYPASS
C9
29
OTP_OV_
BYPASS2
—
—
—
—
—
—
—
Reserved
CA
2A
OTP_UV_
BYPASS1
—
Reserved
—
—
Reserved
OTP_SW3_
UVBYPASS
OTP_SW2_
UVBYPASS
OTP_SW1_
UVBYPASS
CB
2B
OTP_UV_
BYPASS2
—
—
—
—
—
—
—
Reserved
CC
2C
OTP_ILIM_
BYPASS1
—
Reserved
—
—
Reserved
OTP_SW3_
ILIMBYPASS
OTP_SW2_
ILIMBYPASS
OTP_SW1_
ILIMBYPASS
CD
2D
OTP_ILIM_
BYPASS2
—
—
—
—
—
—
—
Reserved
CE
2E
OTP_PROG_
IDH
—
—
—
—
OTP_PROG_ID11
OTP_PROG_ID10
OTP_PROG_ID9
OTP_PROG_ID8
CF
2F
OTP_PROG_
IDL
OTP_PROG_ID7
OTP_PROG_ID6
OTP_PROG_ID5
OTP_PROG_ID4
OTP_PROG_ID3
OTP_PROG_ID2
OTP_PROG_ID1
OTP_PROG_ID0
D0
30
OTP DEBUG1
—
—
—
—
—
—
—
BGMON_BYPASS
D1
31
OTP SW
COMP1
—
—
OTP_SW2_GM_COMP[2:0]
OTP_SW1_GM_COMP[2:0]
D2
32
OTP SW
COMP2
—
—
Reserved
OTP_SW3_GM_COMP[2:0]
D3
33
OTP SW
COMP3
Reserved
Reserved
—
—
—
—
—
—
D4
34
OTP SW RAMP
Reserved
OTP_SW3DVS_RAMP[1:0]
OTP_SW2DVS_RAMP[1:0]
OTP_SW1DVS_RAMP[1:0]
D5
35
OTP_S0_CRC_
LSB
OTP_S0_CRC_LSB[7:0]
D6
36
OTP_SO_
CRC_MSB
OTP_SO_CRC_MSB[7:0]



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