Z86D7308HSC datasheet(68/92 Pages) ZILOG

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Z86D73

40/44/48-Pin Low-Voltage IR OTP

PS019402-1103

Any Port 2 bit defined as an output drives the corresponding

input to the default state. This condition allows the remaining

inputs to control the AND/OR function. Refer to SMR2 register

on page 63 for other recover sources.

Stop-Mode Recovery Delay Select (D5)

This bit, if low, disables the 5 ms RESET delay after Stop-Mode Recovery. The

default configuration of this bit is 1. If the “fast” wake up is selected, the Stop-

Mode Recovery source must be kept active for at least 5 TpC.

Stop-Mode Recovery Edge Select (D6)

A 1 in this bit position indicates that a High level on any one of the recovery

sources wakes the Z86D73 from STOP Mode. A 0 indicates Low level recovery.

The default is 0 on POR.

Cold or Warm Start (D7)

This bit is read only. It is set to 1 when the device is recovered from Stop Mode.

The bit is set to 0 when the device reset is other than Stop Mode Recovery (SMR).

Table 17. Stop-Mode Recovery Source

SMR:432

Operation

Description of Action

POR and/or external reset recovery

001

Reserved

P31 transition

P32 transition

P33 transition

P27 transition

Logical NOR of P20 through P23

Logical NOR of P20 through P27

Note:

Z86D7308HSC Datasheet(PDF) 68 Page - Zilog, Inc.