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Z86D7308HSC Datasheet(PDF) 69 Page - Zilog, Inc. |
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Z86D7308HSC Datasheet(HTML) 69 Page - Zilog, Inc. |
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69 / 92 page ![]() Z86D73 40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y 63 Stop-Mode Recovery Register 2 (SMR2) This register determines the mode of Stop-Mode Recovery for SMR2 (Figure 37). SMR2 (0F) DH Figure 37. Stop-Mode Recovery Register 2 ((0F) DH:D2–D4, D6 Write Only) If SMR2 is used in conjunction with SMR, either of the specified events causes a Stop-Mode Recovery. Port pins configured as outputs are ignored as an SMR or SMR2 recovery source. For example, if the NAND or P23–P20 is selected as the recovery source and P20 is configured as an output, the remaining SMR pins (P23–P21) form the NAND equation. D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR Only * 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level * * 0Low * 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery. * Default setting after reset * * At the XOR gate input Note: |
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