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Z86D7308HSC Datasheet(PDF) 20 Page - Zilog, Inc. |
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Z86D7308HSC Datasheet(HTML) 20 Page - Zilog, Inc. |
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20 / 92 page ![]() Z86D73 40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y 14 Table 7. External I/O or Memory Read and Write Timing (Preliminary) TA = 0 °C to +70 °C 8.0 MHz* No Symbol Parameter VCC Min Max Units Notes 1 TdA(AS) Address Valid to AS Rising Delay 2.0 V 3.6 V 55 55 ns ns 2 2 TdAS(A) AS Rising to Address Float Delay 2.0 V 3.6 V 70 70 ns ns 2 2 3 TdAS(DR) AS Rising to Read Data Required Valid 2.0 V 3.6 V 400 400 ns ns 1, 2 4TwAS AS Low Width 2.0 V 3.6 V 80 80 ns ns 2 5 Td Address Float to DS Falling 2.0 V 3.6 V 0 0 ns ns 6TwDSR DS (Read) Low Width 2.0 V 3.6 V 300 300 ns ns 1, 2 7TwDSW DS (Write) Low Width 2.0 V 3.6 V 165 165 ns ns 1, 2 8 TdDSR(DR) DS Falling to Read Data Required Valid 2.0 V 3.6 V 260 260 ns ns 1, 2 9 ThDR(DS) Read Data to DS Rising Hold Time 2.0 V 3.6 V 0 0 ns ns 2 10 TdDS(A) DS Rising to Address Active Delay 2.0 V 3.6 V 85 95 ns ns 2 11 TdDS(AS) DS Rising to AS Falling Delay 2.0 V 3.6 V 60 70 ns ns 2 12 TdR/W(AS) R/W Valid to AS Rising Delay 2.0 V 3.6 V 70 70 ns ns 2 13 TdDS(R/W) DS Rising to R/W Not Valid 2.0 V 3.6 V 70 70 ns ns 2 14 TdDW(DSW) Write Data Valid to DS Falling (Write) Delay 2.0 V 3.6 V 80 80 ns ns 2 15 TdDS(DW) DS Rising to Write Data Not Valid Delay 2.0 V 3.6 V 70 80 ns ns 2 16 TdA(DR) Address Valid to Read Data Required Valid 2.0 V 3.6 V 475 475 ns ns 1, 2 |
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