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Z86D7308HSC Datasheet(PDF) 59 Page - Zilog, Inc. |
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Z86D7308HSC Datasheet(HTML) 59 Page - Zilog, Inc. |
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59 / 92 page ![]() Z86D73 40/44/48-Pin Low-Voltage IR OTP PS019402-1103 P R E L I M I N A R Y 53 During Ping-Pong Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alter- nately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers reach the terminal count. Interrupts The Z86D73 feature six different interrupts (Table 15). The interrupts are maskable and prioritized (Figure 31). The six sources are divided as follows: three sources are claimed by Port 3 lines P33–P31 and two by the counter/timers (Table 15). The Interrupt Mask Register (globally or individually) enables or dis- ables the five interrupt requests. |
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