Z86D7308HSC datasheet(32/92 Pages) ZILOG

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Z86D73

40/44/48-Pin Low-Voltage IR OTP

PS019402-1103

Comparator Inputs

In analog mode, P31 and P32 have a comparator front end. The comparator refer-

ence is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its

corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and

P33) as indicated in Figure 13 on page 23. In digital mode, P33 is used as D3 of

the Port 3 input register, which then generates IRQ1.

Comparators are powered down by entering Stop Mode. For

P31–P33 to be used in a Stop-Mode Recovery source, these

inputs must be placed into digital mode.

Comparator Outputs

These channels can be programmed to be output on P34 and P37 through the

PCON register.

RESET (Input, Active Low)

Reset initializes the MCU and is accomplished either through Power-On, Watch-

Dog Timer, Stop-Mode Recovery, Low-Voltage detection, or external reset. During

Power-On Reset and Watch-Dog Timer Reset, the internally generated reset

drives the reset pin Low for the POR time. Any devices driving the external reset

line need to be open-drain in order to avoid damage from a possible conflict dur-

ing reset conditions. Pull-up is provided internally.

Functional Description

The Z86D73 incorporates special functions to enhance the Z8’s functionality in

consumer and battery-operated applications.

Program Memory

The Z86D73 addresses 32 KB of OTP memory. The first 12 bytes are reserved for

interrupt vectors. These locations contain the five 16-bit vectors that correspond to

the five available interrupts.

RAM

The Z86D73 device features 256 bytes of RAM. See Figure 15.

Note:

Z86D7308HSC Datasheet(PDF) 32 Page - Zilog, Inc.