Z86D7308HSC datasheet(61/92 Pages) ZILOG

61 / 92 page

Z86D73

40/44/48-Pin Low-Voltage IR OTP

PS019402-1103

When more than one interrupt is pending, priorities are resolved by a programma-

ble priority encoder controlled by the Interrupt Priority Register. An interrupt

machine cycle is activated when an interrupt request is granted. As a result, all

subsequent interrupts are disabled, and the Program Counter and Status Flags

are saved. The cycle then branches to the program memory vector location

reserved for that interrupt. All Z86D73 interrupts are vectored through locations in

the program memory. This memory location and the next byte contain the 16-bit

address of the interrupt service routine for that particular interrupt request. To

accommodate polled interrupt systems, interrupt inputs are masked, and the Inter-

rupt Request register is polled to determine which of the interrupt requests require

service.

An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is

mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge

triggered. These interrupts are programmable by the user. The software can poll

to identify the state of the pin.

Programming bits for the Interrupt Edge Select are located in the IRQ Register

(R250), bits D7 and D6. The configuration is indicated in Table 16.

Table 15. Interrupt Types, Sources, and Vectors

Name

Source

Vector Location

Comments

IRQ0

P32

0,1

External (P32), Rising Falling Edge Triggered

IRQ1

P33

2,3

External (P33), Falling Edge Triggered

IRQ2

P31, TIN 4,5

External (P31), Rising Falling Edge Triggered

IRQ3

T16

6,7

Internal

IRQ4

8,9

Internal

IRQ5

LVD

10,11

Internal

Table 16. IRQ Register*

IRQ

Interrupt Edge

IRQ2 (P31)

IRQ0 (P32)

R/F

Notes: F = Falling Edge; R = Rising Edge

*In stop mode, the comparators are turned off.

Z86D7308HSC Datasheet(PDF) 61 Page - Zilog, Inc.

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