P87LPC779FDH datasheet(51/74 Pages) PHILIPS

51 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

51 of 74

9397 750 13213

As data bits come in from the right, 1s shift out to the left. When the start bit arrives at

the leftmost position in the shift register (which in mode 1 is a 9-bit register), it ﬂags

the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal

to load SBUF and RB8, and to set RI, will be generated if, and only if, the following

conditions are met at the time the ﬁnal shift pulse is generated:

1. R1 = 0, and

2. Either SM2 = 0, or the received stop bit = 1.

If either of these two conditions is not met, the received frame is irretrievably lost. If

both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and

RI is activated. At this time, whether the above conditions are met or not, the unit

goes back to looking for a 1-to-0 transition in RxD.

8.15.10

More about UART Modes 2 and 3

Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (1). On transmit, the

9th data bit (TB8) can be assigned the value of ‘0’ or ‘1’. On receive, the 9th data bit

goes into RB8 in SCON. The baud rate is programmable to either 1

⁄

16 or

⁄

32 of the

CPU clock frequency in Mode 2. Mode 3 may have a variable baud rate generated

from Timer1.

Figures 25 and 26 show a functional diagram of the serial port in Modes 2 and 3. The

receive portion is exactly the same as in Mode 1. The transmit portion differs from

Mode 1 only in the 9th bit of the transmit shift register.

Transmission is initiated by any instruction that uses SBUF as a destination register.

The ‘write to SBUF’ signal also loads TB8 into the 9th bit position of the transmit shift

commences at S1P1 of the machine cycle following the next rollover in the

divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16

counter, not to the ‘write to SBUF’ signal.)

The transmission begins with activation of SEND, which puts the start bit at TxD. One

bit time later, DATA is activated, which enables the output bit of the transmit shift

a ‘1’ (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros

are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the

left. When TB8 is at the output position of the shift register, then the stop bit is just to

the left of TB8, and all positions to the left of that contain zeros. This condition ﬂags

the TX Control unit to do one last shift and then deactivate SEND and set TI. This

occurs at the 11th divide-by-16 rollover after ‘write to SBUF.’

Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is

sampled at a rate of 16 times whatever baud rate has been established. When a

transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is

written to the input shift register.

At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the

value of R-D. The value accepted is the value that was seen in at least 2 of the 3

samples. If the value accepted during the ﬁrst bit time is not 0, the receive circuits are

P87LPC779FDH Datasheet(PDF) 51 Page - NXP Semiconductors

P87LPC779FDH Datasheet(HTML) 51 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL