P87LPC779FDH datasheet(28/74 Pages) PHILIPS

28 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

28 of 74

9397 750 13213

8.8.1

External interrupt inputs

The P87LPC779 has two individual interrupt inputs as well as the Keyboard Interrupt

function. The latter is described separately elsewhere in this section. The two

interrupt inputs are identical to those present on the standard 80C51 microcontroller.

The external sources can be programmed to be level-activated or transition-activated

by setting or clearing bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is

triggered by a detected low at the INTn pin. If ITn = 1, external interrupt n is edge

triggered. In this mode if successive samples of the INTn pin show a high in one cycle

and a low in the next cycle, interrupt request ﬂag IEn in TCON is set, causing an

interrupt request.

Since the external interrupt pins are sampled once each machine cycle, an input high

or low should hold for at least 6 CPU Clocks to ensure proper sampling. If the

external interrupt is transition-activated, the external source has to hold the request

pin high for at least one machine cycle, and then hold it low for at least one machine

cycle. This is to ensure that the transition is seen and that interrupt request ﬂag IEn is

set. IEn is automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-activated, the external source must hold the request

active until the requested interrupt is actually generated. If the external interrupt is still

asserted when the interrupt service routine is completed another interrupt will be

generated. It is not necessary to clear the interrupt ﬂag IEn when the interrupt is level

sensitive, it simply tracks the input pin level.

If an external interrupt is enabled when the P87LPC779 is put into Power-down or

Idle mode, the interrupt will cause the processor to wake up and resume operation.

Refer to Section 8.12 “Power reduction modes” on page 38 for details.

A/D Converter

ADCI

005Bh

EAD (IEN1.4)

IP1H.4, IP1.4

Yes

Comparator 1 interrupt

CMF1

0063h

EC1 (IEN1.5)

IP1H.5, IP1.5

Yes

Timer I interrupt

0073h

ETI (IEN1.7)

IP1H.7, IP1.7

13 (lowest)

Table 19:

Summary of interrupts…continued

Description

Interrupt

Flag Bit(s)

Vector

Address

Interrupt

Enable Bit(s)

Interrupt

Priority

Arbitration

Ranking

Power-down

Wake-up

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