P87LPC779FDH datasheet(15/74 Pages) PHILIPS

15 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

15 of 74

9397 750 13213

When the A/D is operated from the RCCLK while the CPU is running from another

clock source, 3 or 4 machine cycles are used to synchronize A/D operation. The time

can range from a minimum of 3 machine cycles (at the CPU clock rate) + 108 RC

clocks to a maximum of 4 machine cycles (at the CPU clock rate) + 112 RC clocks.

Example A/D conversion times at various CPU clock rates are shown in Table 8. In

the table, maximum times for RCCLK = 1 use an RC clock frequency of 6 MHz.

Minimum times for RCCLK = 1 use an RC clock frequency of. Nominal time assume

an ideal RC clock frequency of 6 MHz and an average of 3.5 machine cycles at the

CPU clock rate.

8.4.1

The A/D in Power-down and Idle modes

While using the CPU clock as the A/D clock source, the Idle mode may be used to

conserve power and/or to minimize system noise during the conversion. CPU

operation will resume and Idle mode terminate automatically when a conversion is

complete if the A/D interrupt is active. In Idle mode, noise from the CPU itself is

eliminated, but noise from the oscillator and any other on-chip peripherals that are

running will remain.

The CPU may be put into Power-down mode when the A/D is clocked by the on-chip

RC oscillator (RCCLK = 1). This mode gives the best possible A/D accuracy by

eliminating most on-chip noise sources.

If the Power-down mode is entered while the A/D is running from the CPU clock

(RCCLK = 0), the A/D will abort operation and will not wake up the CPU. The

contents of DAC0 will be invalid when operation does resume.

Table 8:

Example A/D conversion times

CPU clock rate

RCCLK = 0

RCCLK = 1

minimum

nominal

maximum

32 kHz

563.4

µs

659

µs

757

µs

1 MHz

186

µs

32.4

µs

39.3

µs

48.9

µs

4 MHz

46.5

µs

18.9

µs

23.6

µs

30.1

µs

11.0592 MHz

16.8

µs16 µs

20.2

µs

27.1

µs

12 MHz

15.5

µs

15.9

µs

20.1

µs

26.9

µs

16 MHz

11.6

µs

15.5

µs

19.7

µs

26.4

µs

20 MHz

9.3

µs

15.3

µs

19.4

µs

26.1

µs

Fig 5.

A/D converter connections.

002aaa616

AD0 (P0.3)

AD1 (P0.4)

A/D CONVERTER

AD2 (P0.5)

AD3 (P0.6)

ADCON

DAC0

ADCON

DAC0

(A/D result, read DAC0)

VREF+ = VDD

VREF- = VSS

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