P87LPC779FDH datasheet(25/74 Pages) PHILIPS

25 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

25 of 74

9397 750 13213

8.7.6

Regarding software response time

Because the P87LPC779 can run at 20 MHz, and because the I2C-bus interface is

optimized for high-speed operation, it is quite likely that an I2C-bus service routine will

sometimes respond to DRDY (which is set at a rising edge of SCL) and write I2DAT

before SCL has gone low again. If XDAT were applied directly to SDA, this situation

would produce an I2C-bus protocol violation. The programmer need not worry about

this possibility because XDAT is applied to SDA only when SCL is low.

Conversely, a program that includes an I2C-bus service routine may take a long time

to respond to DRDY. Typically, an I2C-bus routine operates on a ﬂag-polling basis

during a message, with interrupts from other peripheral functions enabled. If an

interrupt occurs, it will delay the response of the I2C-bus service routine. The

programmer need not worry about this very much either, because the I2C-bus

hardware stretches the SCL low time until the service routine responds. The only

constraint on the response is that it must not exceed the Timer I time-out.

Table 14:

I2DAT - I2C-bus data register (address D9H) bit description

Bit

Symbol

Access

Description

RDAT

The most recently received data bit, captured from SDA at

every rising edge of SCL. Reading I2DAT also clears DRDY

and the Transmit Active state.

XDAT

Sets the data for the next transmitted bit. Writing I2DAT also

clears DRDY and sets the Transmit Active state.

6 to 0 -

Reserved for future use. Should not be set to ‘1’ by user

programs.

Table 15:

I2CFG - I2C-bus conﬁguration register (address C8h) bit allocation

Not bit addressable; Reset value: 00H

Bit

Symbol

SLAVEN

MASTRQ

CLRTI

TIRUN

CT1

CT0

Table 16:

I2CFG - I2C-bus conﬁguration register (address C8h) bit description

Bit

Symbol

Description

SLAVEN

Slave Enable. Writing a ‘1’ this bit enables the slave functions of

the I2C-bus subsystem. If SLAVEN and MASTRQ are ‘0’, the

I2C-bus hardware is disabled. This bit is cleared to ‘0’ by reset and

by an I2C-bus time-out.

MASTRQ

Master Request. Writing a ‘1’ to this bit requests mastership of the

I2C-bus. If a transmission is in progress when this bit is changed

from ‘0’ to ‘1’, action is delayed until a stop condition is detected. A

start condition is sent and DRDY is set (thus making ATN = ‘1’ and

generating an I2C-bus interrupt). When a master wishes to release

mastership status of the I2C-bus, it writes a ‘1’ to XSTP in I2CON.

MASTRQ is cleared by an I2C-bus time-out.

CLRTI

Writing a ‘1’ to this bit clears the Timer I overﬂow ﬂag. This bit

position always reads as a ‘0’.

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