P87LPC779FDH datasheet(59/74 Pages) PHILIPS

59 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

59 of 74

9397 750 13213

8.16.1

Watchdog feed sequence

If the Watchdog timer is running, it must be fed before it times out in order to prevent

a chip reset from occurring. The Watchdog feed sequence consists of ﬁrst writing the

value 1Eh, then the value E1h to the WDRST register. An example of a Watchdog

feed sequence is shown below.

WDFeed:

mov

WDRST,#1eh

; First part of Watchdog feed sequence.

mov

WDRST,#0e1h

; Second part of Watchdog feed sequence.

The two writes to WDRST do not have to occur in consecutive instructions. An

incorrect Watchdog feed sequence does not cause any immediate response from the

Watchdog timer, which will still time out at the originally scheduled time if a correct

feed sequence does not occur prior to that time.

After a chip reset, the user program has a limited time in which to either feed the

Watchdog timer or change the timeout period. When a low CPU clock frequency is

used in the application, the number of instructions that can be executed before the

Watchdog overﬂows may be quite small.

8.16.2

Watchdog reset

If a Watchdog reset occurs, the internal reset is active for approximately one

microsecond. If the CPU clock was still running, code execution will begin

immediately after that. If the processor was in Power-down mode, the Watchdog reset

will start the oscillator and code execution will resume after the oscillator is stable.

Table 43:

WDCON - Watchdog timer control register (address A7H) bit allocation

Not bit addressable; Reset value: 30H for a Watchdog reset; 10H for other reset sources if the

Watchdog is enabled via the WDTE conﬁguration bit; 00H for other reset sources if the

Watchdog is disabled via the WDTE conﬁguration bit.

Bit

Symbol

WDOVF

WDRUN

WDCLK

WDS2

WDS1

WDS0

Table 44:

WDCON - Watchdog timer control register (address A7H) bit description

Bit

Symbol

Description

7, 6

Reserved for future use. Should not be set to ‘1’ by user programs.

WDOVF

Watchdog timer overﬂow ﬂag. Set when a Watchdog reset or timer

overﬂow occurs. Cleared when the Watchdog is fed.

WDRUN

Watchdog run control. The Watchdog timer is started when

WDRUN = 1 and stopped when WDRUN = 0. This bit is forced to

‘1’ (Watchdog running) if the WDTE conﬁguration bit = 1.

WDCLK

Watchdog clock select. The Watchdog timer is clocked by CPU

clock / 6 when WDCLK = 1 and by the Watchdog RC oscillator

when WDCLK = 0. This bit is forced to ‘0’ (using the Watchdog RC

oscillator) if the WDTE conﬁguration bit = 1.

2-0

WDS2-0

Watchdog rate select.

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