P87LPC779FDH datasheet(22/74 Pages) PHILIPS

22 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

22 of 74

9397 750 13213

8.7.1

I2C-bus interrupts

If I2C-bus interrupts are enabled (EA and EI2 are both set to 1), an I2C-bus interrupt

will occur whenever the ATN ﬂag is set by a start, stop, arbitration loss, or data ready

condition (refer to the description of ATN following). In practice, it is not efﬁcient to

operate the I2C-bus interface in this fashion because the I2C-bus interrupt service

routine would somehow have to distinguish between hundreds of possible conditions.

Also, since I2C-bus can operate at a fairly high rate, the software may execute faster if

the code simply waits for the I2C-bus interface.

Typically, the I2C-bus interrupt should only be used to indicate a start condition at an

idle slave device, or a stop condition at an idle master device (if it is waiting to use the

I2C-bus). This is accomplished by enabling the I2C-bus interrupt only during the

aforementioned conditions.

[1]

Due to the manner in which bit addressing is implemented in the 80C51 family, the I2CON register

should never be altered by use of the SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to

the fact that read and write functions of this register are different. Testing of I2CON bits via the JB and

JNB instructions is supported.

Table 11:

I2CON - I2C-bus control register (address D8H) bit allocation

Bit addressable[1]; Reset value: 81H

Bit

Symbol (R)

RDAT

ATN

DRDY

ARL

STR

STP

MASTER

Symbol (W)

CXA

IDLE

CDR

CARL

CSTR

CSTP

XSTR

XSTP

Table 12:

I2CON - I2C-bus control register (address D8H) bit description

Bit Symbol

Access Description

RDAT

The most recently received data bit

CXA

Clears the transmit active ﬂag

ATN

ATN = 1 if any of the ﬂags DRDY, ARL, STP, or STP = 1

IDLE

In the I2C-bus slave mode, writing a ‘1’ to this bit causes the I2C-bus

hardware to ignore the bus until it is needed again

DRDY

Data Ready ﬂag, set when there is a rising edge on SCL

CDR

Writing a ‘1’ to this bit clears the DRDY ﬂag

ARL

Arbitration Loss ﬂag, set when arbitration is lost while in the transmit

mode

CARL

Writing a ‘1’ to this bit clears the CARL ﬂag

STR

Start ﬂag, set when a start condition is detected at a master or

non-idle slave

CSTR

Writing a ‘1’ to this bit clears the STR ﬂag

STP

Stop ﬂag, set when a stop condition is detected at a master or

non-idle slave

CSTP

Writing a ‘1’ to this bit clears the STP ﬂag

MASTER R

Indicates whether this device is currently as bus master

XSTR

Writing a ‘1’ to this bit causes a repeated start condition to be

generated

Undeﬁned

XSTP

Writing a ‘1’ to this bit causes a stop condition to be generated

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