P87LPC779FDH datasheet(24/74 Pages) PHILIPS

24 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

24 of 74

9397 750 13213

8.7.4

Writing I2CON

Typically, for each bit in an I2C-bus message, a service routine waits for ATN = 1.

Based on DRDY, ARL, STR, and STP, and on the current bit position in the message,

it may then write I2CON with one or more of the following bits, or it may read or write

the I2DAT register.

CXA — Writing a ‘1’ to ‘Clear Xmit Active’ clears the Transmit Active state. (Reading

the I2DAT register also does this.)

8.7.5

Regarding Transmit Active

Transmit Active is set by writing the I2DAT register, or by writing I2CON with

XSTR = 1 or XSTP = 1. The I2C-bus interface will only drive the SDA line low when

Transmit Active is set, and the ARL bit will only be set to ‘1’ when Transmit Active is

set. Transmit Active is cleared by reading the I2DAT register, or by writing I2CON with

CXA = 1. Transmit Active is automatically cleared when ARL is ‘1’.

IDLE — Writing ‘1’ to ‘IDLE’ causes a slave’s I2C-bus hardware to ignore the I2C-bus

until the next start condition (but if MASTRQ is ‘1’, then a stop condition will cause

this device to become a master).

CDR — Writing a ‘1’ to ‘Clear Data Ready' clears DRDY. (Reading or writing the

I2DAT register also does this.)

CARL — Writing a ‘1’ to ‘Clear Arbitration Loss’ clears the ARL bit.

CSTR — Writing a ‘1’ to ‘Clear STaRt’ clears the STR bit.

CSTP — Writing a ‘1’ to ‘Clear SToP’ clears the STP bit. Note that if one or more of

DRDY, ARL, STR, or STP is ‘1’, the low time of SCL is stretched until the service

routine responds by clearing them.

XSTR — Writing ‘1’s to ‘Xmit repeated STaRt’ and CDR tells the I2C-bus hardware to

send a repeated start condition. This should only be at a master. Note that XSTR

need not and should not be used to send an ‘initial’ (non-repeated) start; it is sent

automatically by the I2C-bus hardware. Writing XSTR = ‘1’ includes the effect of

writing I2DAT with XDAT = ‘1’; it sets Transmit Active and releases SDA to HIGH

during the SCL low time. After SCL goes HIGH, the I2C-bus hardware waits for the

suitable minimum time and then drives SDA low to make the start condition.

XSTP — Writing 1s to ‘Xmit SToP’ and CDR tells the I2C-bus hardware to send a stop

condition. This should only be done at a master. If there are no more messages to

initiate, the service routine should clear the MASTRQ bit in I2CFG to ‘0’ before writing

XSTP with ‘1’. Writing XSTP = ‘1’ includes the effect of writing I2DAT with XDAT = ‘0’;

it sets Transmit Active and drives SDA low during the SCL low time. After SCL goes

HIGH, the I2C-bus hardware waits for the suitable minimum time and then releases

SDA to HIGH to make the stop condition.

Table 13:

I2DAT - I2C-bus data register (address D9H) bit allocation

Not bit addressable; Reset value: xxH

Bit

Symbol (R)

RDAT

-------

Symbol (W)

XDAT

-------

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