P87LPC779FDH datasheet(18/74 Pages) PHILIPS

18 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

18 of 74

9397 750 13213

negative input (selectable from a pin or an internal reference voltage). Otherwise the

output is a zero. Each comparator may be conﬁgured to cause an interrupt when the

output value changes.

8.6.1

Comparator conﬁguration

Each comparator has a control register, CMP1 for comparator 1 and CMP2 for

comparator 2. The control registers are identical and are shown in Tables 9 and 10.

The overall connections to both comparators are shown in Figure 7. There are eight

possible conﬁgurations for each comparator, as determined by the control bits in the

corresponding CMPn register: CPn, CNn, and OEn. These conﬁgurations are shown

in Figure 8. The comparators function down to a VDD of 3.0 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are

not guaranteed to be stable for 10

µs. The corresponding comparator interrupt should

not be enabled during that time, and the comparator interrupt ﬂag must be cleared

before the interrupt is enabled in order to prevent an immediate interrupt service.

Table 9:

CMPn - Comparator control registers CMP1 and CMP2 (address ACh for

CMP1, ADh for CMP2) bit allocation

Not bit addressable; Reset value: 00H

Bit

Symbol

CEn

CPn

CNn

OEn

COn

CMFn

Table 10:

CMPn - Comparator control registers CMP1 and CMP2 (address ACh for

CMP1, ADh for CMP2) bit description

Bit

Symbol

Description

7, 6

Reserved for future use. Should not be set to ‘1’ by user programs.

CEn

Comparator enable. When set by software, the corresponding

comparator function is enabled. Comparator output is stable 10

µs

after CEn is ﬁrst set.

CPn

Comparator positive input select. When ‘0’, CINnA is selected as

the positive comparator input. When ‘1’, CINnB is selected as the

positive comparator input.

CNn

Comparator negative input select. When ‘0’, the comparator

reference pin CMPREF is selected as the negative comparator

input. When ‘1’, the internal comparator reference Vref is selected

as the negative comparator input.

OEn

Output enable. When ‘1’, the comparator output is connected to

the CMPn pin if the comparator is enabled (CEn = 1). This output

is asynchronous to the CPU clock.

COn

Comparator output, synchronized to the CPU clock to allow

reading by software. Cleared when the comparator is disabled

(CEn = 0).

CMFn

Comparator interrupt ﬂag. This bit is set by hardware whenever the

comparator output COn changes state. This bit will cause a

hardware interrupt if enabled and of sufﬁcient priority. Cleared by

software and when the comparator is disabled (CEn = 0).

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