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P87LPC779FDH Datasheet(PDF) 27 Page - NXP Semiconductors

Part # P87LPC779FDH
Description  CMOS single-chip 8-bit 80C51 microcontroller with 128-byte data RAM, 8 kB OTP
PDF  74 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P87LPC779FDH Datasheet(HTML) 27 Page - NXP Semiconductors

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Philips Semiconductors
P87LPC779
CMOS single-chip 8-bit microcontroller
Product data
Rev. 02 — 03 May 2004
27 of 74
9397 750 13213
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.8 Interrupts
The P87LPC779 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the P87LPC779’s many interrupt sources. The
P87LPC779 supports up to 13 interrupt sources.
Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA,
which disables all interrupts at once.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service
routine in progress can be interrupted by a higher priority interrupt, but not by another
interrupt of the same or lower priority. The highest priority interrupt service cannot be
interrupted by any other interrupt source. So, if two requests of different priority levels
are received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. This is called the arbitration ranking.
Note that the arbitration ranking is only used to resolve simultaneous requests of the
same priority level.
Table 19 summarizes the interrupt sources, flag bits, vector addresses, enable bits,
priority bits, arbitration ranking, and whether each interrupt may wake up the CPU
from Power-down mode.
Table 18:
CT1, CT0 values
CT1, CT0
Min Time Count
(Machine Cycles)
CPU Clock Max
(for 100 kHz I2C-bus)
Timeout Period
(Machine Cycles)
1 0
7
8.4 MHz
1023
0 1
6
7.2 MHz
1022
0 0
5
6.0 MHz
1021
1 1
4
4.8 MHz
1020
Table 19:
Summary of interrupts
Description
Interrupt
Flag Bit(s)
Vector
Address
Interrupt
Enable Bit(s)
Interrupt
Priority
Arbitration
Ranking
Power-down
Wake-up
External Interrupt 0
IE0
0003h
EX0 (IEN0.0)
IP0H.0, IP0.0
1 (highest)
Yes
Timer0 Interrupt
TF0
000Bh
ET0 (IEN0.1)
IP0H.1, IP0.1
4
No
External Interrupt 1
IE1
0013h
EX1 (IEN0.2)
IP0H.2, IP0.2
7
Yes
Timer1 Interrupt
TF1
001Bh
ET1 (IEN0.3)
IP0H.3, IP0.3
10
No
Serial Port Tx and Rx
TI & RI
0023h
ES (IEN0.4)
IP0H.4, IP0.4
12
No
Brownout Detect
BOD
002Bh
EBO (IEN0.5)
IP0H.5, IP0.5
2
Yes
I2C-bus Interrupt
ATN
0033h
EI2 (IEN1.0)
IP1H.0, IP1.0
5
No
KBI Interrupt
KBF
003Bh
EKB (IEN1.1)
IP1H.1, IP1.1
8
Yes
Comparator 2 interrupt
CMF2
0043h
EC2 (IEN1.2)
IP1H.2, IP1.2
11
Yes
Watchdog Timer
WDOVF
0053h
EWD (IEN0.6)
IP0H.6, IP0.6
3
Yes



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