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NRF9160-SICA-R7 Datasheet(PDF) 381 Page - Nordic Semiconductor |
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NRF9160-SICA-R7 Datasheet(HTML) 381 Page - Nordic Semiconductor |
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381 / 400 page  Debug and trace Register Offset Security Description TASKS_CLOCKSTART 0x000 Start all trace and debug clocks. TASKS_CLOCKSTOP 0x004 Stop all trace and debug clocks. ENABLE 0x500 Enable debug domain and aquire selected GPIOs PSEL.TRACECLK 0x504 Pin configuration for TRACECLK PSEL.TRACEDATA0 0x508 Pin configuration for TRACEDATA[0] PSEL.TRACEDATA1 0x50C Pin configuration for TRACEDATA[1] PSEL.TRACEDATA2 0x510 Pin configuration for TRACEDATA[2] PSEL.TRACEDATA3 0x514 Pin configuration for TRACEDATA[3] TRACEPORTSPEED 0x518 Clocking options for the Trace Port debug interface Reset behavior is the same as debug components This register is retained. Table 111: Register overview 9.3.1.1 TASKS_CLOCKSTART Address offset: 0x000 Start all trace and debug clocks. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A W TASKS_CLOCKSTART Start all trace and debug clocks. Trigger 1 Trigger task 9.3.1.2 TASKS_CLOCKSTOP Address offset: 0x004 Stop all trace and debug clocks. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A W TASKS_CLOCKSTOP Stop all trace and debug clocks. Trigger 1 Trigger task 9.3.1.3 ENABLE Address offset: 0x500 Enable debug domain and aquire selected GPIOs Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A RW ENABLE DISABLED 0 Disable debug domain and release selected GPIOs ENABLED 1 Enable debug domain and aquire selected GPIOs 4418_1315 v2.0 381 |
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