NRF9160-SICA-R7 datasheet(370/400 Pages) NORDIC

370 / 400 page

Debug and trace

Debugging capability

UICR.APPROTECT.PALL

UICR.SECUREAPPROTECT.PALL

Secure and non-secure

code

Unprotected

Non-secure code only

Unprotected

Protected

No debugging possible

Protected

Table 104: Debugger access control

If a RAM or flash region has its permission set to allow code execution, the content of this region will

be visible to the debugger even if the read permission is not set. This allows a debugger to display the

content of the code being executed. For more about how to configure permissions, please refer to SPU —

System protection unit on page 259.

9.1.2 DAP - Debug access port

An external debugger can access the device via the debug access port (DAP).

The DAP implements a standard ARM CoreSight serial wire debug port (SW-DP). The SW-DP implements

the serial wire debug (SWD) protocol that is a two-pin serial interface, see SWDCLK and SWDIO illustrated

in figure Debug and trace overview on page 369.

In addition to the default access port in the application CPU (AHB-AP), the DAP includes a custom control

access port (CTRL-AP), described in more detail in CTRL-AP - Control access port on page 372.

Note:

• The SWDIO line has an internal pull-up resistor.

• The SWDCLK line has an internal pull-down resistor.

There are several access ports that connect to different parts of the system. An overview is given in the

table below.

AP ID

Type

Description

AHB-AP

Application subsystem access port

APB-AP

CoreSight subsystem access port

CTRL-AP

Application subsystem control access port

Table 105: Access port overview

The standard ARM components are documented in ARM CoreSight SoC-400 Technical Reference Manual,

revision r3p2. The control access port (CTRL-AP) is proprietary, and described in more detail in CTRL-AP -

Control access port on page 372.

9.1.3 Debug interface mode

Before the external debugger can access the CPU's access port (AHB-AP) or the control access port (CTRL-

AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP.

As long as the debugger is requesting power via CxxxPWRUPREQ, the device will be in debug interface

mode. Otherwise, the device is in normal mode. When a debug session is over, the external debugger

must make sure to put the device back into normal mode and then a pin reset should be performed. The

reason is that the overall power consumption is higher in debug interface mode compared to normal

mode.

Some peripherals behave differently in debug interface mode compared to normal mode. The differences

are described in more detail in the chapters of the affected peripherals.

4418_1315 v2.0

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