NRF9160-SICA-R7 datasheet(373/400 Pages) NORDIC

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Debug and trace

page 41 respectively. The debugger can use the register APPROTECT.STATUS on page 376 to read the

status of secure and non-secure access port protection.

CTRL-AP has the following features:

• Soft reset

• Erase all

• Mailbox interface

• Debug of protected devices

9.2.1 Reset request

The debugger can request the device to perform a soft reset.

Use the register RESET on page 375 to request a soft reset. Once the soft reset is performed, the reset

reason is accessible on the on-chip firmware through the RESETREAS register. For more information about

the soft reset, see Reset on page 56.

9.2.2 Erase all

The Erase all function lets the debugger trigger an erase of flash, user information configuration registers

(UICR), RAM, all peripheral settings, and also removes the access port protection.

To trigger an erase all function, the debugger writes to the register ERASEALL on page 375. The register

ERASEALLSTATUS on page 375 will read as busy for the duration of the operation. After the next reset,

the access port protection is removed.

If the debugger performs an erase all function on a slave MCU, the erase sequence will always erase the

application MCU first, independently of how the application is protected, before erasing the slave MCU.

Erase all protection

It is possible to prevent the debugger from performing an erase all operation by writing to the

UICR.ERASEPROTECT register. Once the register is configured and the device is reset, the CTRL-AP

ERASEALL operation is disabled, and all flash write and erase operations are restricted to the firmware. In

addition, it is still possible to write/erase from the debugger as long as the UICR.APPROTECT register is not

set.

Note: Setting the UICR.ERASEPROTECT register only affects the erase all operation and not the

debugger access.

The register ERASEPROTECT.STATUS on page 376 holds the status for erase protection.

9.2.3 Mailbox interface

CTRL-AP implements a mailbox interface which enables the CPU to communicate with a debugger over the

SWD interface.

The mailbox interface consists of a transmit register MAILBOX.TXDATA on page 377 with its

corresponding status register MAILBOX.TXSTATUS on page 377, and a receive register MAILBOX.RXDATA

on page 377 with its corresponding status register MAILBOX.RXSTATUS on page 377. Status bits in the

TXSTATUS/RXSTATUS registers are set and cleared automatically when the TXDATA/RXDATA registers are

written to and read from, independently of the direction.

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NRF9160-SICA-R7 Datasheet(PDF) 373 Page - Nordic Semiconductor