| Electronic Components Datasheet Search |
|
NRF9160-SICA-R7 Datasheet(PDF) 375 Page - Nordic Semiconductor |
|
|
|||||||||||||||||||||||||||||
NRF9160-SICA-R7 Datasheet(HTML) 375 Page - Nordic Semiconductor |
|
375 / 400 page ![]() Debug and trace Register Offset Description ERASEPROTECT.STATUS 0x018 This is the status register for the UICR ERASEPROTECT configuration. ERASEPROTECT.DISABLE 0x01C This register disables ERASEPROTECT and performs ERASEALL. MAILBOX.TXDATA 0x020 Data sent from the debugger to the CPU. MAILBOX.TXSTATUS 0x024 This register shows a status that indicates if data sent from the debugger to the CPU has been read. MAILBOX.RXDATA 0x028 Data sent from the CPU to the debugger. MAILBOX.RXSTATUS 0x02C This register shows a status that indicates if data sent from the CPU to the debugger has been read. IDR 0x0FC CTRL-AP Identification Register, IDR Table 107: Register overview 9.2.5.1.1 RESET Address offset: 0x000 System reset request This register is automatically deactivated by writing Erase to ERASEALL, it is then kept inactive until a reset source affecting the debug system is asserted. See Reset behavior on page 57. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A RW RESET System reset request and status NoReset 0 Write to release reset Reading '0' means reset is not active Reset 1 Write to hold reset Reading '1' means reset is active 9.2.5.1.2 ERASEALL Address offset: 0x004 Perform a secure erase of the device, where flash, SRAM and UICR will be erased in sequence. The device will be returned to factory default settings upon next reset. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A W ERASEALL Return device to factory default settings NoOperation 0 No operation Erase 1 Erase flash, SRAM, and UICR in sequence 9.2.5.1.3 ERASEALLSTATUS Address offset: 0x008 This is the status register for the ERASEALL operation. 4418_1315 v2.0 375 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |