HC705JB2GRSSLASHH datasheet(101/128 Pages) NXP

101 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

EPROM

REV 1.1

11-1

SECTION 11

EPROM

This section describes erasable programmable read-only memory (EPROM)

programming.

11.1

EPROM

The on-chip user EPROM consists of 2048 bytes of EPROM from $1600 to

$1DFF and 16 bytes of user vectors from $1FF0 to $1FFF.

The bootloader ROM and vectors are located from $1E00 to $1FEF.

12 of the user vectors, $1FF4-$1FFF, are dedicated to reset and interrupt vectors.

The four remaining locations, $1FF0-$1FF3, are reserved for test functions. The

Mask Option Register is located at $01FF.

11.2

BOOTLOADER

This program (contained in an on-chip boot ROM) handles copying of user code

from an external EPROM into the on-chip EPROM. The bootloader function does

not have to be done from an EPROM, but can be done from a host.

11.2.1 Bootloader Mode

Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin is

at VTST and the PB0 pin is at logic zero. The bootloader performs one

programming pass at 1ms per byte then does a verify pass.

The user code must be a one-to-one correspondence with the internal EPROM

addresses.

Table 11-1. Operation Mode Condition After Reset

RESET Pin

IRQ/VPP

PB0/TCAP

MODE

VSS to VDD

Single-Chip (Normal)

VTST

VSS

Bootloader

VTST = 2 x VDD

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JB2GRS/H Datasheet(PDF) 101 Page - NXP Semiconductors

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