HC705JJ7GRSSLASHD datasheet(137/230 Pages) NXP

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MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Simple Serial Interface

General Release Specification — MC68HC705JJ7/MC68HC705JP7

Section 9. Simple Serial Interface

9.1 Contents

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

9.3

SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

9.3.1

Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

9.3.2

Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . .140

9.3.3

Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . .140

9.4

SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

9.4.1

SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . .141

9.4.2

SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . .144

9.4.3

SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . .145

9.2 Introduction

The simple synchronous serial I/O port (SIOP) subsystem is designed to

provide efficient serial communications with peripheral devices or other

MCUs. SIOP is implemented as a 3-wire master/slave system with serial

clock (SCK), serial data input (SDI), and serial data output (SDO). A

block diagram of the SIOP is shown in Figure 9-1.

The SIOP subsystem shares its input/output pins with port B. When the

SIOP is enabled (SPE bit set in the SCR), the port B data direction and

data registers are bypassed by the SIOP. The port B data direction and

data registers will remain accessible and can be altered by the

application software, but these actions will not affect the SIOP

transmitted or received data.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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