ST25R3916B datasheet(57/165 Pages) STMICROELECTRONICS

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DS13541 Rev 7

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ST25R3916B ST25R3917B

Application information

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Direct command chaining

As shown in Figure 21, direct commands with immediate execution can be followed by

another SPI mode (Read, Write or FIFO) without deactivating the BSS signal in between.

Figure 21. SPI communication: direct command chaining

Loading data in the PT_Memory (PT_Memory load)

Loading data into the PT_Memory is similar to loading data into the FIFO. There are three

mode patterns available to load data into three different parts of the PT_memory, as

indicated in Table 12. The first byte following the mode/address pattern is stored in the

location detailed in Table 12, for consecutive bytes the address is automatically incremented

and data are stored to consecutive addresses.

The user must take care that the number of loaded bytes fits the size of the selected

PT_memory area, not to overwrite data in the following PT_memory areas.

4.3.4

I2C interface

The I2C address is 50h.This interface supports:

•

Standard mode (100 kHz)

•

Fast mode (400 kHz)

•

Fast mode Plus (1 MHz)

•

High speed mode (3.4 MHz).

Table 13 summarizes the I2C interface signals.

Writing data to addressable registers (Register Write mode)

After the I2C slave address the address of the register to be written is sent using the same

then followed by one or more data bytes. If more than one data byte is sent, the data is

stored in subsequent registers starting form the initial register address by incrementing the

target address by one for each new data byte.

MS51649V1

BSS

Direct command

Read, Write or FIFO mode

Table 13. I2C interface and interrupt signal lines

Name

Signal

Signal level

Description

I2C_EN

Digital input

CMOS

Pull to VDD_D for I2C operation

MISO (SDA)

Digital output

I2C data line

SCLK (SCL)

Digital input

I2C clock

IRQ

Digital output

Active high - Interrupt output pin

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