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ST25R3916B Datasheet(PDF) 69 Page - STMicroelectronics

Part # ST25R3916B
Description  NFC reader for payment, consumer and industrial applications
PDF  165 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST25R3916B Datasheet(HTML) 69 Page - STMicroelectronics

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DS13541 Rev 7
69/165
ST25R3916B ST25R3917B
Application information
164
4.5
Registers
The ST25R3916B and ST25R3917B have two register spaces, each of them consists of up
to 64 registers with address ranging from 00h to 3Fh:
1.
register space A (Rs-A), see Table 18
2.
register space B (Rs-B), see Table 19.
There are two types of registers implemented in the ST25R3916B and ST25R3917B:
1.
configuration registers: used to configure the device, can be written and read through
the SPI or I2C interfaces
2.
display registers: read only (RO), contain information about the state of the device.
Registers are set to their default value at power-up and after sending the direct command
Set default. Bits set as RFU must be kept at their reset values unless otherwise specified.
7A0
Analog voltage of
amplitude measurement
D0
Analog voltage of phase
measurement
m_amp_ana and
m_phase_ana in
Rs-A, Reg 3Bh
define which is
active
BD0
Digital output of AM
correlation data signal
D0
Digital output of AM
correlation collision/start
detection signal
-
CD0
Digital output of PM
correlation data signal
D0
Digital output of PM
correlation collision/start
detection signal
-
DA0
Analog output of AM
correlation signal
A0
Correlation digitizing
threshold for AM channel
-
EA0
Analog output of PM
correlation signal
A0
Correlation digitizing
threshold for PM channel
-
1. Set en=1 and rx_en=1 in Operation control register before enabling tana<3:0> test modes.
Table 17. Test access register - Signal selection of TAD1 and TAD2 pins(1) (continued)
tana3:0
(hex)
Pin TAD1
Pin TAD2
Type
Functionality
Type
Functionality
Comment
Table 18. List of registers - Space A
Type
Address (hex)
Register space A (Rs-A)
IO configuration
00
IO configuration register 1
01
IO configuration register 2
Operation control and
mode definition
02
Operation control register
03
Mode definition register
04
Bit rate definition register



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