SN250 datasheet(70/130 Pages) STMICROELECTRONICS

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Functional description—application modules

SN250

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Serialized SC2 SPI transmit data is driven to the output pin MOSI. SC2 SPI master data is

received from the input pin MISO. To generate slave select signals to SPI slave devices,

other GPIO pins have to be used and their assertion must be controlled by software.

Characters transmitted and received are passed through transmit and receive FIFOs. The

transmit and receive FIFOs are 4 bytes deep. These FIFOs are accessed under software

control by accessing the SC2_DATA data register or under hardware control using a DMA

controller.

When a transmit character is written to the (empty) transmit FIFO, the register bit

SC_SPITXIDLE

in the SC2_SPISTAT register clears and indicates that not all characters

are transmitted yet. Further transmit characters can be written to the transmit FIFO until it is

full, which causes the register bit SC_SPITXFREE in the SC2_SPISTAT register to clear.

After shifting out one transmit character to the MOSI pin, space for one transmit character

becomes available in the transmit FIFO. This causes the register bit SC_SPITXFREE in the

SC2_SPISTAT

empties, which causes the register bit SC_SPITXIDLE in the SC2_SPISTAT register to get

set also.

Any character received is stored in the (empty) receive FIFO. The register bit

SC_SPIRXVAL

in the SC2_SPISTAT register is set to indicate that not all received

characters are read out from receive FIFO. If software or DMA is not reading from the

receive FIFO, the receive FIFO will store up to 4 characters. Any further reception is

Table 24.

SC2 SPI master mode formats

SC2_SPICFG

Frame Format

210

SC2-3M

mode

210

SC2-3M

mode

210

SC2-3M

mode

210

SC2-3M

mode

211

SC2-3M

mode

Same as above except LSB first instead of MSB first

SC2-4S

mode

Illegal

SC2-2 mode

Illegal

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