SN250 datasheet(76/130 Pages) STMICROELECTRONICS

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Functional description—application modules

SN250

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Characters received and transmitted are passed through receive and transmit FIFOs. The

SC2 I2C master transmit and receive FIFOs are 1 byte deep. These FIFOs are accessed

under software control.

(Re)start and stop segments are initiated by setting the register bits SC_I2CSTART or

SC_I2CSTOP

in the SC2_I2CCTRL1 register, followed by waiting until they have cleared.

Alternatively, the register bit SC_I2CCMDFIN in the SC2_I2CSTAT can be used for waiting.

For initiating a transmit segment, the data has to be written to the SC2_DATA data register,

followed by setting the register bit SC_I2CSEND in the SC2_I2CCTRL1 register, and

completed by waiting until it clears. Alternatively, the register bit SC_I2CTXFIN in the

SC2_I2CSTAT

can be used for waiting.

A receive segment is initiated by setting the register bit SC_I2CRECV in the SC2_I2CCTRL1

Alternatively, the register bit SC_I2CRXFIN in the SC2_I2CSTAT can be used for waiting.

Now the register bit SC_I2CRXNAK in the SC2_I2CSTAT register indicates if a NACK or

ACK was received from an I2C slave device.

Interrupts are generated on the following events:

●

Bus command (SC_I2CSTART/SC_I2CSTOP) completed (0 to 1 transition of

SC_I2CCMDFIN

)

●

Character transmitted and slave device responded with NACK

●

Character transmitted (0 to 1 transition of SC_I2CTXFIN)

●

Character received (0 to 1 transition of SC_I2CRXFIN)

●

Received and lost character while receive FIFO was full (Receive overrun error)

●

Transmitted character while transmit FIFO was empty (Transmit underrun error)

To generate interrupts to the CPU, the interrupt masks in the INT_SC2CFG and INT_CFG

SC2-4M mode Illegal

SC2-4A mode Illegal

Table 27.

I2C master segment formats (continued)

SC2_I2CCTR

Frame Segments

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