SN250 datasheet(26/130 Pages) STMICROELECTRONICS

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Functional description—system modules

SN250

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6.8

Reset detection

The SN250 contains multiple reset sources. The reset event is logged into the reset source

causes are detected:

●

Power-on-Reset

●

Watchdog

●

PC rollover

●

Software reset

●

Core Power Dip

6.9

Power-on-Reset (POR)

Each voltage domain (1.8V Digital Core Supply VDD_CORE and Pads Supply VDD_PADS)

has a power-on-reset (POR) cell.

The VDD_PADS POR cell holds the always-powered high-voltage domain in reset until the

following conditions have been met:

●

The high-voltage Pads Supply VDD_PADS voltage rises above a threshold.

●

The internal RC clock starts and generates three clock pulses.

●

The 1.8V POR cell holds the main digital core in reset until the regulator output voltage

rises above a threshold.

Additionally, the digital domain counts 1,024 clock edges on the 24MHz crystal before

releasing the reset to the main digital core.

Table 11 lists the features of the SN250 POR circuitry.

6.10

Clock sources

The SN250 integrates three oscillators: a high-frequency 24MHz crystal oscillator, an

optional low-frequency 32.768kHz crystal oscillator, and a low-frequency internal 10kHz RC

oscillator.

6.10.1

High-frequency crystal oscillator

The integrated high-frequency crystal oscillator requires an external 24MHz crystal with an

accuracy of ± 40ppm. Based upon the application Bill of Materials and current consumption

requirements, the external crystal can cover a range of ESR requirements. For a lower ESR,

the cost of the crystal increases but the overall current consumption decreases. Likewise,

Table 11.

POR specifications

Parameter

Min.

Typ.

Max.

Unit

VDD_PADS POR release

1.0

1.2

1.4

VDD_PADS POR assert

0.5

0.6

0.7

1.8V POR release

1.35

1.5

1.65

1.8V POR hysteresis

0.08

0.1

0.12

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