SN250 datasheet(46/130 Pages) STMICROELECTRONICS

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Functional description—application modules

SN250

46/130

Characters transmitted and received are passed through transmit and receive FIFOs. The

transmit and receive FIFOs are 4 bytes deep. The FIFOs are accessed under software

control by accessing the SC1_DATA data register or under hardware control by the SC1

DMA.

When a transmit character is written to the (empty) transmit FIFO, the register bit

SC1_UARTTXIDLE

in the SC1_UARTSTAT register clears to indicate that not all characters

are transmitted yet. Further transmit characters can be written to the transmit FIFO until it is

full, which causes the register bit SC1_UARTTXFREE in the SC1_UARTSTAT register to clear.

After shifting one transmit character to the TXD pin, space for one transmit character

becomes available in the transmit FIFO. This causes the register bit SC1_UARTTXFREE in

the SC1_UARTSTAT register to get set. After all characters are shifted out, the transmit FIFO

empties, which causes the register bit SC1_UARTTXIDLE in the SC1_UARTSTAT register to

get set.

A received character is stored with its parity and frame error status in the receive FIFO. The

received characters are read out from the receive FIFO. The error status of a received byte

is available with the register bits SC1_UARTPARERR and SC1_UARTFRMERR in the

SC1_UARTSTAT

FIFO to a memory buffer, it checks the stored parity and frame error status flags. When an

error is flagged, the SC1_RXERRA/B register is updated, marking the offset to the first

received character with parity or frame error.

When the 4-character receive FIFO contains 3 characters, flow control needs to be used to

avoid an overflow event. One method is to use software handshaking by transmitting

reserved XON/XOFF characters which are interpreted by the transmitting terminal to pause

further transmissions (to the receive FIFO). Another method is to use hardware

handshaking using XOFF assertion through the RTS signal.

Table 20.

Configuration table for the UART module

SC1_UARTCFG

GPIO_CFG[7:4] GPIO-Pin Function

SC1_MODE

SC1_UARTFLOW SC1_UARTAUTO

SC1_UARTRTS

SC1-2 mode

TXD/RXD

output/input

SC1-2 mode

Illegal

0/1

SC1-4A mode

TXD/RXD/CTS

output/input/input

RTS output =

ON/OFF

SC1-4A mode

TXD/RXD/CTS

output/input/input

RTS output = ON if 2

or more bytes will fit

in receive buffer

SC1-4A mode

Reserved

SC1-4A mode

Illegal

SC1-3M mode

Illegal

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