SN250 datasheet(31/130 Pages) STMICROELECTRONICS

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SN250

Functional description—application modules

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Functional description—application modules

In Application Mode, access to privileged areas are blocked while access to application-

specific modules such as GPIO, Serial Controllers (SC1 and SC2), General Purpose

Timers, ADC, and Event Manager are enabled.

7.1

GPIO

The SN250 has 17 multi-purpose GPIO pins that can be configured in a variety of ways. All

pins have the following programmable features:

●

Selectable as input, output, or bi-directional.

●

Output can be totem pole, used as open drain or open source output for wired-OR

applications.

●

Can have internal pull-up or pull-down.

The information flow between the GPIO pin and its source are controlled by separate GPIO

Data registers. The GPIO_INH and GPIO_INL registers report the input level of the GPIO

pins. The GPIO_DIRH and GPIO_DIRL registers enable the output signals for the GPIO

Pins. The GPIO_PUH and GPIO_PUL registers enable pull-up resistors while GPIO_PDH and

GPIO_PDL

registers enable pull-down resistors on the GPIO Pins. The GPIO_OUTH and

GPIO_OUTL

control the output level.

Instead of changing the entire contents to the OUT/DIR registers with one write access, a

limited change can be applied. Writing to the GPIO_SETH/L or GPIO_DIRSETH/L register

changes individual register bits from 0 to 1, while data bits that are already 1 are maintained.

Writing to the GPIO_CLRH/L or GPIO_DIRCLRH/L register changes individual register bits

from 1 to 0, while data bits that are already 0 are maintained.

Note that the value read from GPIO_OUTH/L, GPIO_SETH/L, and GPIO_CLRH/L registers

may not reflect the current pin state. To observe the pin state, the GPIO_INH/L registers

should be read.

All registers controlling the GPIO pin definitions are unaffected by power cycling the main

core voltage (VDD_CORE).

SN250 Datasheet(PDF) 31 Page - STMicroelectronics