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HC705MC4GRS/D Datasheet(PDF) 143 Page - NXP Semiconductors |
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HC705MC4GRS/D Datasheet(HTML) 143 Page - NXP Semiconductors |
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143 / 180 page  Core Timer Computer Operating Properly (COP) Watchdog Reset General Release Specification Core Timer 12.4 Computer Operating Properly (COP) Watchdog Reset The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 12-2. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP timeout is done by writing a 0 to bit 0 of address $0FF0. When the COP is cleared, only the final divide-by-eight stage (output of the RTI) is cleared. This function is a mask option. Table 12-2. Minimum COP Reset Times RT1:RT0 Minimum COP Reset at Bus Frequency: 16.384 kHz 3.0 MHz fop 00 7 sec 38.2 ms 7 × (RTI Rate) 01 14 sec 76.5 ms 7 × (RTI Rate) 10 28 sec 153.0 ms 7 × (RTI Rate) 11 56 sec 305.9 ms 7 × (RTI Rate) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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