HC705MC4GRSSLASHD datasheet(43/180 Pages) NXP

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Interrupts

Hardware Interrupts

General Release Specification

Interrupts

The interrupt mask bit operates by inhibiting the interrupt signal

after the

appropriate interrupt request latch. This feature allows the interrupt to be

recognized and latched even if the mask is set.

When the IRQ input goes to the active level for at least one tILIH, a logic

1 is latched internally to signify an interrupt has been requested. When

the MCU completes its current instruction, the interrupt latch is tested. If

the interrupt latch contains a logic 1, and the interrupt mask bit (I bit) in

the condition code register and the IRQ mask bit (IRQM) in the ISCR are

both clear, then the MCU can begin the interrupt sequence. The state of

the interrupt latch is reflected in the interrupt request bit (REQ) in the

ISCR and is cleared automatically during interrupt processing. See

Figure 4-2.

IRQ interrupt requests are acknowledged automatically and cleared

during interrupt processing. It also may be cleared through software by

setting the acknowledge bit in the ISCR. Setting this bit is a one-shot

operation and will not affect subsequent interrupt operation. The action

of clearing the acknowledge bit will clear the request bit. This allows the

programmer the option to cancel spurious interrupts that occur while the

interrupt mask bits are set. This may be necessary in systems where it

is desirable to prevent redundant (ghost) entries to the interrupt service

routine (where the interrupt mask is eventually cleared).

NOTE:

The IRQM is cleared (enabled) during reset, although no interrupts can

occur until the interrupt mask bit of the CCR is cleared. The interrupt

mask bit (I bit) of the CCR is set during reset. The interrupt request

latches also are cleared during reset.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D Datasheet(PDF) 43 Page - NXP Semiconductors