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HC705MC4GRS/D Datasheet(PDF) 89 Page - NXP Semiconductors |
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HC705MC4GRS/D Datasheet(HTML) 89 Page - NXP Semiconductors |
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89 / 180 page  16-Bit Timer Input Capture General Release Specification 16-Bit Timer Reading the LSB of the input capture register pair (ICRL1, ICRL2) does not inhibit transfer of the free-running counter. Again, minimum pulse periods are ones that allow software to read the LSB of the register pair (ICRL1, ICRL2) and perform needed operations. There is no conflict between reading the LSB (ICRL1, ICRL2) and the free-running counter transfer since they occur on opposite edges of the internal clock. Figure 9-10. State Timing Diagram for Input Capture INTERNAL TIMER T00 T01 T10 T11 INPUT CAPTURE 16-BIT $FFEB $FFED $FFEE $FFEC NOTE: INPUT CAPTURE PREVIOUSLY CAPTURED VALUE $FFED INPUT CAPTURE INPUT CAPTURE $FFEF If the input capture edge occurs in the shaded area between T10 states, then the input capture flag becomes set during the next T11 state. BUS CLOCK CLOCKS COUNTER EDGE LATCH REGISTER FLAG Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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