HC705MC4GRSSLASHD datasheet(74/180 Pages) NXP

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Analog Subsystem

MC68HC705MC4 — Rev. 2.0

Analog Subsystem

8.5 Digital Section

The following subsections describe the digital section of this subsystem.

8.5.1 Conversion Times

Each channel of conversion takes 32 clock cycles, which must be at a

frequency equal to or greater than 1 MHz. For applications in which the

bus speed is below 1 MHz, the A/D internal RC oscillator must be

enabled.

8.5.2 Multi-Channel Operation

In user mode, a multiplexer allows the single A/D converter to select one

of eight analog signals, two of which are VREFH and VREFL. The eight

pins of port C are input signals to the multiplexer.

8.5.3 Unused A/D Inputs as I/O

When the A/D system is enabled, two pins, VREFH (PC6) and VREFL

(PC7), are automatically assumed to have their dedicated functions. The

channel select bits define which port C pin will be used as the analog in

pin and overrides any control from the port C I/O logic by forcing that pin

as the input to the analog circuitry. The port C pins that are not selected

by the channel select bits [CH3:0], are controlled by the port C I/O logic,

and thus can be used as general-purpose I/O. Writes to port C will not

have any effect on the selected channel.

NOTE:

The DDR bits corresponding to an A/D channel used by the application

must be cleared. For example, AD2 shares a pin with PC2, so the

DDRC2 bit must be cleared (unless this is the only channel the A/D ever

selects). This is to ensure that the port output value held in the port C

data register is not driven out of the pin when the A/D has selected

another channel for conversion.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D Datasheet(PDF) 74 Page - NXP Semiconductors