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HC705MC4GRS/D Datasheet(PDF) 45 Page - NXP Semiconductors |
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HC705MC4GRS/D Datasheet(HTML) 45 Page - NXP Semiconductors |
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45 / 180 page  Interrupts Hardware Interrupts General Release Specification Interrupts ACK — IRQ Interrupt Request Acknowledge This bit is write only and will always read as a logic 0. Writing a logic 1 to this bit will acknowledge the interrupt by clearing the corresponding interrupt request bit. NOTE: The use of separate request and acknowledge bits allows the safe use of read-modify-write instructions (for example, BSET and BCLR) on the ISCR register. Figure 4-3. Interrupt Hardware Structure NOTE: When the edge- and level-sensitive mask option is selected, the voltage applied to the IRQ pin must return to the inactive state before the RTI instruction in the interrupt service routine is executed. If the IRQ pin remains in the active level, the interrupt service routine will be re-entered after the RTI is executed. Setting the ACK bit will have no effect under these circumstances. ACK REQ CLEAR Q D VDD INTERRUPT IRQ EDGE EDGE- AND LEVEL-SENSITIVE IRQS IRQM Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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