HC705MC4GRSSLASHD datasheet(91/180 Pages) NXP

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16-Bit Timer

Timer Control Register

General Release Specification

16-Bit Timer

TCMP/TCAP1

Bit 3, when set, enables the TCMP function, when clear, the TCAP1

function. Reset clears this bit. When set it enables the TCMP output

latch value to be output to the port pin and disables the edge detect

of TCAP1. When clear, it disables the TCMP output latch from the port

pin and enables the edge detect of TCAP1. Note that this bit has no

effect on the setting of OCF and ICF1.

NOTE:

The input capture 1 and the output compare functions share the same

data register and are, therefore, mutually exclusive. For example, the

output compare function is not available (including interrupts) when input

capture 1 is enabled.

IEDG1 — Input Capture Edge Select 1

Bit 2 selects which edge of the input capture signal will trigger a

transfer of the contents of the free-running counter registers to the

input capture registers (ICRH1, ICRL1). Clearing this bit will select the

falling edge, setting it selects the rising edge.

IEDG2 — Input Capture Edge Select 2

Bit 1 selects which edge of the input capture signal will trigger a

transfer of the contents of the free-running counter registers to the

input capture registers (ICRH2, ICRL2). Clearing this bit will select the

falling edge, setting it selects the rising edge.

OLVL — Output compare Output level Select

Bit 0 selects the output level (high or low) that is clocked into the

output compare output latch at the next successful output compare.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705MC4GRS/D Datasheet(PDF) 91 Page - NXP Semiconductors